Type | Instance | Vendor | Component | |
---|---|---|---|---|
Processor | mipsle1 | mips.ovpworld.org | mips32_r1r5 | 34Kc |
Peripheral | Core_Board_SDRAM_promInit | mips.ovpworld.org | SmartLoaderLinux | |
Peripheral | sysControl | marvell.ovpworld.org | GT6412x | |
Peripheral | PIIX4 | intel.ovpworld.org | 82371EB | |
Peripheral | PIIX4-IDE | intel.ovpworld.org | PciIDE | |
Peripheral | PCI_PM | intel.ovpworld.org | PciPM | |
Peripheral | PCI_NET | amd.ovpworld.org | 79C970 | |
Peripheral | intCtrlMaster | intel.ovpworld.org | 8259A | |
Peripheral | pciBrD_intCtrlMaster_io | ovpworld.org | DynamicBridge | |
Peripheral | pciBrD_intCtrlMaster_elcr | ovpworld.org | DynamicBridge | |
Peripheral | intCtrlSlave | intel.ovpworld.org | 8259A | |
Peripheral | pciBrD_intCtrlSlave_io | ovpworld.org | DynamicBridge | |
Peripheral | pciBrD_intCtrlSlave_elcr | ovpworld.org | DynamicBridge | |
Peripheral | _SUPERIO_REG_ | ovpworld.org | SerInt | |
Peripheral | pciBrD__SUPERIO_REG__bport1 | ovpworld.org | DynamicBridge | |
Peripheral | vga | cirrus.ovpworld.org | GD5446 | |
Peripheral | pciBrD_vga_config | ovpworld.org | DynamicBridge | |
Peripheral | ps2if | intel.ovpworld.org | Ps2Control | |
Peripheral | pciBrD_ps2if_config | ovpworld.org | DynamicBridge | |
Peripheral | pit | intel.ovpworld.org | 8253 | |
Peripheral | pciBrD_pit_bport1 | ovpworld.org | DynamicBridge | |
Peripheral | rtc | motorola.ovpworld.org | MC146818 | |
Peripheral | pciBrD_rtc_busPort | ovpworld.org | DynamicBridge | |
Peripheral | uartTTY0 | national.ovpworld.org | 16550 | |
Peripheral | pciBrD_uartTTY0_bport1 | ovpworld.org | DynamicBridge | |
Peripheral | uartTTY1 | national.ovpworld.org | 16550 | |
Peripheral | pciBrD_uartTTY1_bport1 | ovpworld.org | DynamicBridge | |
Peripheral | fd0 | intel.ovpworld.org | 82077AA | |
Peripheral | pciBrD_fd0_bport1 | ovpworld.org | DynamicBridge | |
Peripheral | uartCBUS | mips.ovpworld.org | 16450C | |
Peripheral | maltaFpga | mips.ovpworld.org | MaltaFPGA | |
Peripheral | alphaDisplay | ovpworld.org | Alpha2x16Display | |
Peripheral | pciBrD_alphaDisplay_busPort | ovpworld.org | DynamicBridge | |
Memory | Core_Board_SDRAM | ovpworld.org | ram | |
Memory | Core_Board_SDRAM2 | ovpworld.org | ram | |
Memory | Monitor_Flash | ovpworld.org | ram | |
Memory | vgaMemRegion | ovpworld.org | rom | |
Bus | bus1 | (builtin) | address width:addressbits | |
Bus | busPCI | (builtin) | address width:32 | |
Bus | busPCIReMap | (builtin) | address width:32 | |
Bus | PCIconfigBus | (builtin) | address width:16 | |
Bus | PCIackBus | (builtin) | address width:0 | |
Bus | cascadeBus | (builtin) | address width:3 | |
Bus | flashBus | (builtin) | address width:32 | |
Bridge | pciBr | (builtin) | ||
Bridge | pciMBr | (builtin) | ||
Bridge | map | (builtin) | ||
Bridge | remap1 | (builtin) | ||
Bridge | remap2 | (builtin) | ||
Bridge | high2low | (builtin) |
Information for MipsMalta
This page provides detailed information about the mips.ovpworld.org MipsMalta Virtual Platform / Virtual Prototype.
Licensing
Open Source Apache 2.0
Description
This is a platform representing a MIPS Malta development board.
It provides the peripherals required to boot and run a Linux Operating System.
A single MIPS32 architecture processor is instantiated in this platform.
This instance could be duplicated to instantiate further processors to easily create an SMP platform.
Attributes are provided for configuration of the generic ISA model for a specific processor.
The processor model is configured to operate as a MIPS32 4KEc.
The main SDRAM and Flash memory is modeled using RAM models. Both are initialised in places by the
'SmartLoaderLinux'. The SmartLoaderLinux allows ease of use of changing kernel command lines,
loading an initial ram disk and creating the boot flash(s). The operation of the SmartloaderLinux is configured
using a number of attributes.
The kernel attribute of the SmartLoaderLinux and the imagefile of the processor must be consistent.
NOTE: a non Mips Malta peripheral 'AlphaDisplay16x2' has been defined in this platform definition
to be used for demo purposes. It should be removed if there is a memory error in the address space 0x18000100-0x18000103
If this platform is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
Limitations
Verification has only been carried out using Little Endian memory ordering.
Reference
MIPS Malta User's Manual MD00048-2B-MALTA-USM-1.07.pdf
MIPS Malta-R Development Platform User's Manual MD00627-2B-MALTA_R-USM-01.01.pdf
CoreFPGA User's Manual MD00116-2B-COREFPGA-USM-01.00.pdf
Linux for the MIPS Malta Development Platform User's Guide MD00646-2B-LINUXMALTA-USM-01.03.pdf
Description
Allows the address bits for the main bus to be modified (default 32)
Allows the interrupt pin used on the processor to be modified to select direct interrupts or GIC interrupts (default hwint0)
Location
The MipsMalta virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / module / MipsMalta / 1.0.
Platform Summary
Table 1: Components in platform
Platform Simulation Attributes
Table 2: Platform Simulation Attributes
Attribute | Value | Description |
---|---|---|
stoponctrlc | stoponctrlc | Stop on control-C |
Processor [mips.ovpworld.org/processor/mips32_r1r5/1.0] instance: mipsle1
Processor model type: 'mips32_r1r5' variant '34Kc' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32_r1r5/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_r1r5_34Kc.pdf
Description
MIPS32 Configurable Processor Model
Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features
only MIPS32 Instruction set implemented
MMU Type: Standard TLB
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Vectored interrupts implemented
MIPS16e ASE implemented
MT ASE implemented
DSP ASE implemented
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'mipsle1' it has been instanced with the following parameters:
Table 3: Processor Instance 'mipsle1' Parameters (Configurations)
Parameter | Value | Description |
---|---|---|
endian | little | Select processor endian (big or little) |
simulateexceptions | simulateexceptions | Causes the processor simulate exceptions instead of halting |
mips | 100.0 | The nominal MIPS for the processor |
Table 4: Processor Instance 'mipsle1' Parameters (Attributes)
Parameter Name | Value | Type |
---|---|---|
variant | 34Kc | enum |
vectoredinterrupt | 0 | bool |
config1MMUSizeM1 | 63 | uns32 |
Memory Map for processor 'mipsle1' bus: 'bus1'
Processor instance 'mipsle1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'mipsle1' is connected to bus 'bus1' using master port 'DATA'.
Table 5: Memory Map ( 'mipsle1' / 'bus1' [width: addressbits] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x0 | 0xFFFFFFF | Core_Board_SDRAM | ram |
0x10000000 | 0x1BFFFFFF | pciBr | bridge |
0x1E000000 | 0x1E3FFFFF | map | bridge |
0x1F000000 | 0x1F0008FF | maltaFpga | MaltaFPGA |
0x1F000900 | 0x1F00093F | uartCBUS | 16450C |
0x1F000A00 | 0x1F000FFF | maltaFpga | MaltaFPGA |
0x1FC00000 | 0x1FC0000F | remap1 | bridge |
0x1FC00010 | 0x1FC00013 | Core_Board_SDRAM_promInit | SmartLoaderLinux |
0x1FC00014 | 0x1FFFFFFF | remap2 | bridge |
0x20000000 | 0x5FFFFFFF | Core_Board_SDRAM2 | ram |
0x80000000 | 0xFFFFFFFF | high2low | bridge |
Table 6: Bridged Memory Map ( 'mipsle1' / 'pciBr' / 'busPCI' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
remappable | remappable | PCI_NET | 79C970 |
remappable | remappable | PCI_PM | PciPM |
remappable | remappable | PIIX4-IDE | PciIDE |
remappable | remappable | pciBrD__SUPERIO_REG__bport1 | DynamicBridge |
remappable | remappable | pciBrD_alphaDisplay_busPort | DynamicBridge |
remappable | remappable | pciBrD_fd0_bport1 | DynamicBridge |
remappable | remappable | pciBrD_intCtrlMaster_elcr | DynamicBridge |
remappable | remappable | pciBrD_intCtrlMaster_io | DynamicBridge |
remappable | remappable | pciBrD_intCtrlSlave_elcr | DynamicBridge |
remappable | remappable | pciBrD_intCtrlSlave_io | DynamicBridge |
remappable | remappable | pciBrD_pit_bport1 | DynamicBridge |
remappable | remappable | pciBrD_ps2if_config | DynamicBridge |
remappable | remappable | pciBrD_rtc_busPort | DynamicBridge |
remappable | remappable | pciBrD_uartTTY0_bport1 | DynamicBridge |
remappable | remappable | pciBrD_uartTTY1_bport1 | DynamicBridge |
remappable | remappable | pciBrD_vga_config | DynamicBridge |
remappable | remappable | sysControl | GT6412x |
remappable | remappable | vga | GD5446 |
0x100A0000 | 0x100BFFFF | vgaMemRegion | rom |
Table 7: Bridged Memory Map ( 'mipsle1' / 'map' / 'flashBus' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x1E000000 | 0x1E3FFFFF | Monitor_Flash | ram |
Table 8: Bridged Memory Map ( 'mipsle1' / 'remap1' / 'flashBus' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x1E000000 | 0x1E3FFFFF | Monitor_Flash | ram |
Table 9: Bridged Memory Map ( 'mipsle1' / 'remap2' / 'flashBus' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x1E000000 | 0x1E3FFFFF | Monitor_Flash | ram |
Table 10: Bridged Memory Map ( 'mipsle1' / 'high2low' / 'bus1' [width: addressbits] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x0 | 0xFFFFFFF | Core_Board_SDRAM | ram |
0x10000000 | 0x1BFFFFFF | pciBr | bridge |
0x1E000000 | 0x1E3FFFFF | map | bridge |
0x1F000000 | 0x1F0008FF | maltaFpga | MaltaFPGA |
0x1F000900 | 0x1F00093F | uartCBUS | 16450C |
0x1F000A00 | 0x1F000FFF | maltaFpga | MaltaFPGA |
0x1FC00000 | 0x1FC0000F | remap1 | bridge |
0x1FC00010 | 0x1FC00013 | Core_Board_SDRAM_promInit | SmartLoaderLinux |
0x1FC00014 | 0x1FFFFFFF | remap2 | bridge |
0x20000000 | 0x5FFFFFFF | Core_Board_SDRAM2 | ram |
Net Connections to processor: 'mipsle1'
Table 11: Processor Net Connections ( 'mipsle1' )
Net Port | Net | Instance | Component |
---|---|---|---|
processorinterrupt | i8259Int | intCtrlMaster | 8259A |
Peripheral Instances
Peripheral [mips.ovpworld.org/peripheral/SmartLoaderLinux/1.0] instance: Core_Board_SDRAM_promInit
Reference
MIPS Malta User Manual. MIPS Boot code reference.
Description
Smart peripheral creates memory initialisation for a MIPS32 based Linux kernel boot. Performs the generation of boot code at the reset vector (virtual address 0xbfc00000) of the MIPS32 processor. Loads both the linux kernel and initial ramdisk into memory and patches the boot code to jump to the kernel start. Initialises the MIPS32 registers and Linux command line.
Licensing
Open Source Apache 2.0
Limitations
None
There are no configuration options set for this peripheral instance.
Peripheral [marvell.ovpworld.org/peripheral/GT6412x/1.0] instance: sysControl
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Description
INFO 0x40
MAIN_BUS 0x20
INT_ACK 0x10
PCI_EMPTY 0x08
PCI_CONFIG_MASTER 0x04
Diagnostic levels:
PCI_SLAVE 0x03
Licensing
Open Source Apache 2.0
Description
GT64120 System Controller.
Reference
GT64121A System Controller for RC4650/4700/5000 and RM526X/527X/7000 CPUs Datasheet Revision 1.0 MAR 14, 2000
There are no configuration options set for this peripheral instance.
Peripheral [intel.ovpworld.org/peripheral/82371EB/1.0] instance: PIIX4
Description
PIIX4 PCI configuration controller.
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Licensing
Open Source Apache 2.0
Reference
Intel 82371EB South Bridge Chipset Datasheet
Table 12: Configuration options (attributes) set for instance 'PIIX4'
Attributes | Value |
---|---|
PCIslot | 10 |
Peripheral [intel.ovpworld.org/peripheral/PciIDE/1.0] instance: PIIX4-IDE
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Description
PCI:IDE interface. This forms part of the 82371 PIIX4 chip. It implements 4 IDE interfaces and 2 DMA controllers.
Licensing
Open Source Apache 2.0
Reference
Intel 82371EB South Bridge Chipset Datasheet
Table 13: Configuration options (attributes) set for instance 'PIIX4-IDE'
Attributes | Value |
---|---|
PCIslot | 10 |
PCIfunction | 1 |
Peripheral [intel.ovpworld.org/peripheral/PciPM/1.0] instance: PCI_PM
Description
PCI Power Manager.
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Licensing
Open Source Apache 2.0
Reference
Intel 82371EB South Bridge Chipset Datasheet
Table 14: Configuration options (attributes) set for instance 'PCI_PM'
Attributes | Value |
---|---|
PCIslot | 10 |
PCIfunction | 3 |
Peripheral [amd.ovpworld.org/peripheral/79C970/1.0] instance: PCI_NET
Reference
AMD Am79C973/Am79C975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Datasheet
Limitations
Sufficient is implemented to Boot MIPS Linux and support ethernet TCP/IP services.
Description
diagnosticlevel: bits 0:1 give levels for the network hardware. bits 2:3 give levels for the user:mode SLIRP interface.
Licensing
Open Source Apache 2.0
Description
Implements part of the AMD AM79C97xx series Ethernet devices.
Table 15: Configuration options (attributes) set for instance 'PCI_NET'
Attributes | Value |
---|---|
PCIslot | 11 |
PCIfunction | 0 |
Peripheral [intel.ovpworld.org/peripheral/8259A/1.0] instance: intCtrlMaster
Description
Intel 8259A Programmable Interrupt Controller (PIT).
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Licensing
Open Source Apache 2.0
Reference
Intel 8259A Datasheet. MIPS Malta Platform Reference Guide.
Table 16: Configuration options (attributes) set for instance 'intCtrlMaster'
Attributes | Value |
---|---|
spen | master |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlMaster_io
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 17: Configuration options (attributes) set for instance 'pciBrD_intCtrlMaster_io'
Attributes | Value |
---|---|
spLoAddress | 402653216 |
mpLoAddress | 402653216 |
portSize | 2 |
enableBridge | 1 |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlMaster_elcr
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 18: Configuration options (attributes) set for instance 'pciBrD_intCtrlMaster_elcr'
Attributes | Value |
---|---|
spLoAddress | 402654416 |
mpLoAddress | 402654416 |
portSize | 1 |
enableBridge | 1 |
Peripheral [intel.ovpworld.org/peripheral/8259A/1.0] instance: intCtrlSlave
Description
Intel 8259A Programmable Interrupt Controller (PIT).
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Licensing
Open Source Apache 2.0
Reference
Intel 8259A Datasheet. MIPS Malta Platform Reference Guide.
Table 19: Configuration options (attributes) set for instance 'intCtrlSlave'
Attributes | Value |
---|---|
spen | slave |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlSlave_io
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 20: Configuration options (attributes) set for instance 'pciBrD_intCtrlSlave_io'
Attributes | Value |
---|---|
spLoAddress | 402653344 |
mpLoAddress | 402653344 |
portSize | 2 |
enableBridge | 1 |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_intCtrlSlave_elcr
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 21: Configuration options (attributes) set for instance 'pciBrD_intCtrlSlave_elcr'
Attributes | Value |
---|---|
spLoAddress | 402654417 |
mpLoAddress | 402654417 |
portSize | 1 |
enableBridge | 1 |
Peripheral [ovpworld.org/peripheral/SerInt/1.0] instance: _SUPERIO_REG_
Licensing
Open Source Apache 2.0
Limitations
This is a register description only. The model does not contain any functionality.
Description
The serial interrupt control registers in the FDC 37M817 SuperIO device.
Reference
SMsC FDC 37M817 SuperIO device datasheet
There are no configuration options set for this peripheral instance.
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD__SUPERIO_REG__bport1
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 22: Configuration options (attributes) set for instance 'pciBrD__SUPERIO_REG__bport1'
Attributes | Value |
---|---|
spLoAddress | 402653360 |
mpLoAddress | 402653360 |
portSize | 4 |
enableBridge | 1 |
Peripheral [cirrus.ovpworld.org/peripheral/GD5446/1.0] instance: vga
Description
Cirrus CL GD5446 VGA controller.
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. The VGA peripheral utilises memory mapping. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.
Licensing
Open Source Apache 2.0
Reference
CL-GD5446 Preliminary Databook, Version 2.0, November 1996
Table 23: Configuration options (attributes) set for instance 'vga'
Attributes | Value |
---|---|
scanDelay | 50000 |
PCIslot | 18 |
title | Imperas MIPS32 Malta |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_vga_config
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 24: Configuration options (attributes) set for instance 'pciBrD_vga_config'
Attributes | Value |
---|---|
spLoAddress | 402654128 |
mpLoAddress | 402654128 |
portSize | 48 |
enableBridge | 1 |
Peripheral [intel.ovpworld.org/peripheral/Ps2Control/1.0] instance: ps2if
Description
PS2 Keyboard/Mouse Controller.
Limitations
This is a preliminary model with sufficient functionality to enable Linux to Boot on the MIPS:MALTA platform. Mouse functions are currently turned off.
Licensing
Open Source Apache 2.0
Reference
SMsC FDC37M817 Super I/O Controller Datasheet
Table 25: Configuration options (attributes) set for instance 'ps2if'
Attributes | Value |
---|---|
pollPeriod | 50000 |
grabDisable | 1 |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_ps2if_config
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 26: Configuration options (attributes) set for instance 'pciBrD_ps2if_config'
Attributes | Value |
---|---|
spLoAddress | 402653280 |
mpLoAddress | 402653280 |
portSize | 8 |
enableBridge | 1 |
Peripheral [intel.ovpworld.org/peripheral/8253/1.0] instance: pit
Licensing
Open Source Apache 2.0
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. Not all modes are supported.
Description
Intel 8253 Programmable Interval Timer (PIT)
Reference
Intel 8253 Datasheet. MIPS Malta Platform Reference Guide.
There are no configuration options set for this peripheral instance.
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_pit_bport1
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 27: Configuration options (attributes) set for instance 'pciBrD_pit_bport1'
Attributes | Value |
---|---|
spLoAddress | 402653248 |
mpLoAddress | 402653248 |
portSize | 4 |
enableBridge | 1 |
Peripheral [motorola.ovpworld.org/peripheral/MC146818/1.0] instance: rtc
Description
MC146818 Real:time clock.
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Licensing
Open Source Apache 2.0
Reference
Motorola MC146818AS Datasheet
There are no configuration options set for this peripheral instance.
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_rtc_busPort
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 28: Configuration options (attributes) set for instance 'pciBrD_rtc_busPort'
Attributes | Value |
---|---|
spLoAddress | 402653296 |
mpLoAddress | 402653296 |
portSize | 2 |
enableBridge | 1 |
Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY0
Limitations
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
Values written to the MCR are ignored. Loopback mode is not supported.
Description
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.
Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Description
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Licensing
Open Source Apache 2.0
Description
16550 UART model
Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)
Table 29: Configuration options (attributes) set for instance 'uartTTY0'
Attributes | Value |
---|---|
outfile | uartTTY0.log |
finishOnDisconnect | 1 |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_uartTTY0_bport1
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 30: Configuration options (attributes) set for instance 'pciBrD_uartTTY0_bport1'
Attributes | Value |
---|---|
spLoAddress | 402654200 |
mpLoAddress | 402654200 |
portSize | 8 |
enableBridge | 1 |
Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY1
Limitations
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
Values written to the MCR are ignored. Loopback mode is not supported.
Description
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.
Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Description
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Licensing
Open Source Apache 2.0
Description
16550 UART model
Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)
Table 31: Configuration options (attributes) set for instance 'uartTTY1'
Attributes | Value |
---|---|
outfile | uartTTY1.log |
finishOnDisconnect | 1 |
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_uartTTY1_bport1
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 32: Configuration options (attributes) set for instance 'pciBrD_uartTTY1_bport1'
Attributes | Value |
---|---|
spLoAddress | 402653944 |
mpLoAddress | 402653944 |
portSize | 8 |
enableBridge | 1 |
Peripheral [intel.ovpworld.org/peripheral/82077AA/1.0] instance: fd0
Reference
http://www.buchty.net/casio/files/82077.pdf http://www.alldatasheet.com/datesheet-pdf/pdf/167793/INTEL/82077AA.html
Limitations
Register stubs only.
Licensing
Open Source Apache 2.0
Description
Dummy Floppy Disc Controller.
There are no configuration options set for this peripheral instance.
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_fd0_bport1
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 33: Configuration options (attributes) set for instance 'pciBrD_fd0_bport1'
Attributes | Value |
---|---|
spLoAddress | 402654192 |
mpLoAddress | 402654192 |
portSize | 8 |
enableBridge | 1 |
Peripheral [mips.ovpworld.org/peripheral/16450C/1.0] instance: uartCBUS
Limitations
No modem support (DTR etc).
No modelling of baud:rate.
Description
Note that on start:up, the UART model will block the simulator, pending a connection to the socket.
The serial input/output ports are modelled by socket connection which must be attached to a process outside the simulation environment.
Connects to a bus by a slave port and optionally to a processor by an interrupt signal.
Special version with register addresses for MIPS MALTA C-BUS.
Model of 16550/16450 UART.
Licensing
Open Source Apache 2.0
Limitations
No support for parity.
No means to simulate errors.
Reference
MIPS Malta Datasheet
Table 34: Configuration options (attributes) set for instance 'uartCBUS'
Attributes | Value |
---|---|
outfile | uartCBUS.log |
Peripheral [mips.ovpworld.org/peripheral/MaltaFPGA/1.0] instance: maltaFpga
Description
MIPS MALTA FPGA. Drives Development board functions.
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Licensing
Open Source Apache 2.0
Reference
MIPS Malta User Manual.
Table 35: Configuration options (attributes) set for instance 'maltaFpga'
Attributes | Value |
---|---|
stoponsoftreset | 1 |
Peripheral [ovpworld.org/peripheral/Alpha2x16Display/1.0] instance: alphaDisplay
Limitations
This is not representing a real device and provides simple operations as an example.
Licensing
Open Source Apache 2.0
Description
This is a simple test peripheral creating a 2x16 alphanumeric display.
Reference
This is not based upon a real device
There are no configuration options set for this peripheral instance.
Peripheral [ovpworld.org/peripheral/DynamicBridge/1.0] instance: pciBrD_alphaDisplay_busPort
Licensing
Open Source Apache 2.0
Limitations
The range of the input slave port must not conflict with any exiting port connected to the bus. The output bus width is hard coded to be 32 bits.
Description
DynamicBridge - Dynamically enable/disable a bus bridge from the input slave port to the output master port. The bridge is enabled when the input net is high, disabled when it is low. The size of the port is defined with the portSize parameter. The address on the input slave port is defined by the spLoAddress parameter. The address on the output master port is defined by the mpLoAddress parameter. All three parameters must be specified. The input and output ports may be connected to the same bus.
Reference
This is not based upon the operation of a real device
Table 36: Configuration options (attributes) set for instance 'pciBrD_alphaDisplay_busPort'
Attributes | Value |
---|---|
spLoAddress | 402653440 |
mpLoAddress | 402653440 |
portSize | 4 |
enableBridge | 1 |
Information on the MipsMalta Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: Using OVP models with OSCI SystemC TLM2.0 platforms to gain 200-500 MIPS performance
http://www.ovpworld.org: Using OVP models with OSCI SystemC TLM2.0 platforms to gain 200-500 MIPS performance
http://www.ovpworld.org: ARC Demo Video Presentation
http://www.ovpworld.org: Renesas v850 Bare Metal Video Presentation
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.