The Most Complete Collection of Fast Instruction Set Simulators in the Industry

If you are developing software for a processor where you do not have access to the hardware – then you probably need to have a look at using a simulator to develop your software on. Reasons for not having access to the hardware are many. The most common being that the hardware is not yet designed or built and if this is a new chip then the use of a software model or ISS to get the software development started is essential.

With modern instruction sets and processor architectures it is essential that the code you develop is cross compiled and executed on the correct instruction set. Use of host x86 execution only goes so far for modern embedded processors. Many current embedded processors have DSP instructions or specific architectural instructions that affect CPU operation and these just will not exist in a different host processor. Also maybe you have a binary library of say an ARM or MIPS audio or video codec. This will just not run on an x86 and requires you run it on the correct Instruction Set Architecture (ISA). So running your code on the correct ISA is becoming more and more important to get started with early embedded software development.

An Instruction Set Simulator, or ISS, is often the first simulation product used in an embedded software development project. An ISS allows the development and debug of code for the target architecture on an x86/x64 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.

ISS Overview

Where can an ISS be used in embedded software development?

An ISS can be used by many different developers in different software development roles. Used by application software engineers who need to create software binaries on the latest architectures but who do not need platform components – an ISS can work with a standard debuggers and GUIs which makes it very easy to get started with full source code interactive debugging.

Middleware library developers can also use an ISS when building software libraries for common functions, for example multimedia standards where they code at the assembly level and make extensive use of the processor data path – a debugger/GUI shows detailed assembly and all processor registers.

Test engineers can use an ISS in a regression test environment as it can be used in batch/scripted environments as well as being used interactively.

A key component of an ISS is the detailed CPU models it uses

The Imperas ISS makes use of the Imperas OVP Fast Processor Model library providing access to over 150 different instruction accurate embedded CPU model variants from the Imagination/MIPS 24Kc to the ARM Cortex-A72MPx4 quad core 64 bit processor. The Imperas ISS product package comes with all these CPU models and example usage of them.

With a modern ISS, speeds of up to 1,000 MIPS can be expected on modern desktop PCs.

CPU Model Speed

This site provides information on the industry’s most comprehensive library of extremely fast and efficient Instruction Set Simulators (ISS) using CPU Models of advanced processor cores that work in a variety of simulation environments. The whole focus of these ISS is to enable you to develop embedded software in a more efficient way, with less bugs, and in less time.

See the other pages on this site for more detailed features and usage information on these Instruction Set Simulators (ISS).

Fast CPU Models used in the ISS

These ISS use Fast Processor/CPU Models that can be used in C, C++, or SystemC TLM based platforms which you can develop or you can use existing platform models (virtual platforms) available from several sources (e.g. OVPImperas). Readily available virtual platform models range from simple bare metal models through to full development board models such as the MIPS Malta or ARM Versatile Express.

All the models have been developed in C using OVP technology and for SystemC TLM have been tested to run with all major SystemC simulators: Cadence, Synopsys, Mentor, Carbon, Accellera/OSCI. The models have also been tested with emulators from Synopsys ZeBu, Cadence Palladium, and Aldec. The models run on both Windows and Linux host platforms. Native OVP simulators (use C platforms) are available from Imperas and OVP.

On this site you will see the scope and variety of the Instruction Set Simulators (ISS) available and how easy they are to download and use.

Several companies have downloaded the underlying CPU models and use them within their own internal simulation environments. There are specific APIs to easily allow simulator integration and encapsulation. Cadence working with Imperas is one example.

Imperas ISS uses the Largest CPU Model Library in the Industry

The Imperas ISS just uses the models. To use the ISS you do not need to drill down into any more details of the models, you just use them. However, if you do want to find more about the models or consider using them in your own developed virtual platforms, then there is documentation that explains about the models in general (click to preview) and for each model there is a specific document (click to preview the document for the ARMv8 Cortex-A57MPx4 model) that describes what is available in the model, for example its ports, nets, registers, modes, exceptions, and other configuration/parameter options. On the OVP website there is lot of information about each model (for example click to browse the available information on the ARMv8 Cortex-A57MPx4).

An overview document (click to preview) explains, with the use of examples, how the models are configured and used in SystemC TLM2 platforms. If you are just wanting to use the ISS you will not need to read about SystemC or TLM2 platforms.

In a C or C++/SystemC TLM2 environment, the models are used directly, with no inefficient co-simulation. It is very simple to create homogeneous or heterogenous platforms of advanced processor core models. To see examples of platforms ranging from one to twenty-four cores and for platforms that boot full operating systems like Linux and Android, including SMP, visit the the examples and platforms available from the OVP platforms download area or video area.

If you are building your own platforms, then many models can be instanced in one platform, virtual platform or virtual system prototype – it is easy to build multi-core multi-processor platforms using OVP Fast Processor models.

Faster Models means BUGS ARE FOUND SOONER

The Imperas Instruction Set Simulator (ISS) uses models that run fast, hundreds of millions of instructions per second (MIPS).

If you need maximum available simulation speed from the Fast CPU Models, then you need to find our more about QuantumLeap from Imperas. This uses the parallel resources of the host PC to accelerate the speed of the Instruction Set Simulator (ISS) and can also be used for the platforms you develop yourself.

QuantumLeap from Imperas uses host resources to accelerate simulation throughput

For more information on QuantumLeap parallel simulation acceleration using host resources and to find out how to develop your embedded software at the fastest speeds in the industry, browse the Imperas information.

 


Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS