Information for BareMetalArmCortexMSingle
This page provides detailed information about the arm.ovpworld.org BareMetalArmCortexMSingle Virtual Platform / Virtual Prototype. Table 1: Components in platform
Bare Metal Platform for an ARM Cortex-M series Processor (default Cortex-M3). The bare metal platform instantiates a single ARM Cortex-M series processor instance. The processor operates using little endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The platform can be passed any application compiled to an ARM elf format. It may also be passed a new variant to be used (default Cortex-M3) ./platform.OS.exe --program application.CROSS.elf [ --variant
Open Source Apache 2.0
BareMetal platform for execution of ARM binary files compiled with Linaro 32-bit CrossCompiler toolchain for Cortex-M.
The BareMetalArmCortexMSingle virtual platform is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / platform / BareMetalArmCortexMSingle / 1.0.
Table 1: Components in platform
Platform Simulation Attributes
Table 2: Platform Simulation Attributes
|stoponctrlc||stoponctrlc||Stop on control-C|
Command Line Control of the Platform
Table 3: Platform Built-in Arguments
|allargs||allargs||The Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products|
For example: myplatform.exe -help
Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf
Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.
Processor [arm.ovpworld.org/processor/armm/1.0] instance: cpu1
Processor model type: 'armm' variant 'Cortex-M3' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/armm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_armm_Cortex-M3.pdf
ARMM Processor Model
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
Source of model available under separate Imperas Software License Agreement.
Performance Monitors are not implemented.
Debug Extension and related blocks are not implemented.
Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.
The model is configured with 16 interrupts and 3 priority bits (use override_numInterrupts and override_priorityBits parameters to change these).
Thumb-2 instructions are supported.
MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
SysTick timer is present. Use parameter SysTickPresent to disable it if required.
FPU extension is not present. Use parameter override_MVFR0 to enable it if required.
DSP extension is not present. Use parameter override_InstructionAttributes3 to enable it if required.
Bit-band region is present. Use parameter BitBandPresent to disable it if required.
Many instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.
Equal Target Registers
Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.
Floating Point Load/Store Multiple Lists
Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.
If-Then (IT) Block Constraints
Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.
Use of R13
Use of R13 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows R13 to be used like any other GPR.
Use of R15
Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictableR15" as follows:
Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed.
Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
In this variant, the default value of "unpredictableR15" is "execute".
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 4: Processor Instance 'cpu1' Parameters (Configurations)
|endian||little||Select processor endian (big or little)|
|mips||100||The nominal MIPS for the processor|
|semihostvendor||arm.ovpworld.org||The VLNV vendor name of a Semihost library|
|semihostname||armNewlib||The VLNV name of a Semihost library|
Table 5: Processor Instance 'cpu1' Parameters (Attributes)
Memory Map for processor 'cpu1' bus: 'bus'
Processor instance 'cpu1' is connected to bus 'bus' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus' using master port 'DATA'.
Table 6: Memory Map ( 'cpu1' / 'bus' [width: 32] )
|Lo Address||Hi Address||Instance||Component|
Net Connections to processor: 'cpu1'
There are no nets connected to this processor.
Information on the BareMetalArmCortexMSingle Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: PowerPC Bare Metal Video Presentation
http://www.ovpworld.org: riscvOVPsim. A complete RISC-V ISS for bare-metal software development and Specification Compliance Test Development
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.